The present invention relates to a power supply device and, particularly, to a technology effectively applicable to a semiconductor device and a power supply device for use in electronic equipment or the like.
Conventionally, as a power supply device for use in electronic equipment or the like, a power supply device as shown in FIG. 2 is known. In the power supply device shown in FIG. 2, a direct-current power inputted to an input unit 51, which is configured to include an input capacitor 61, from a direct-current input power source 60 is switched by a switching unit 52 based on a control signal outputted from a driving unit 70. Power is supplied to a load 66 from an output unit 53 configured to include a commutation diode 63 and an output filter 55. Also, a voltage and current outputted to the load 66 are detected by a detecting unit 67. The detected value and a control target value of the load 66 set by a setting unit 68 are compared by a comparing operation unit 69. A control signal based on the comparison result is outputted from the driving unit 70 to the switching unit 52. In this manner, control is performed so that the power supplied to the load coincides with the control target value.
A specific circuit configuration of such a power supply device is shown in FIG. 3. The switching unit 52 includes an active element (for example, a transistor or a MOSFET or the like) 62. The output unit 53 is formed as an output filter including the commutation diode 63, a choke coil 64, and a capacitor 65. A control unit 54 includes the comparing operation unit 69, the setting unit 68, and the driving unit 70. Furthermore, the control unit 54 includes an oscillator circuit not shown and outputs a pulse signal from the driving unit 70 to the active element 62. For this reason, a direct-current voltage Vin from the direct-current input power source 60 to be applied to the active element 62 is switched.
In the power supply device shown in FIG. 3, when the active element 62 is in an ON state, the direct-current power is charged to the choke coil 64 and the capacitor 65 and is also supplied to the load 66. When the active element 62 is in an OFF state, energy charged in the choke coil 64 and the capacitor 65 is supplied via the commutation diode 63 to the load 66.
At this time, in the control unit 54, the comparing operation unit 69 monitors an output voltage Vo detected by the detecting unit 67 and compares the output voltage Vo with the control target value set by the setting unit 68, and the driving unit 70 then outputs a control signal based on the comparison result. For this reason, the ON or OFF state of the active element 62 is controlled so that the power supplied to the load coincides with the control target value. At this time, the output voltage Vo can be represented by the following Equation (1),Vo=Vin×(Ton/T)  (1),where “Vin” is an input direct-current voltage, “T” is a cycle of a pulse signal outputted from the driving unit 70, and “Ton” is a conducting time of the active element 62 in a cycle T. That is, “Ton/T” represents a duty ratio.
Here, on a commutation side of the output unit 53, a diode, which is a passive element as shown in FIG. 3, is normally used. However, the commutation diode 63 has a current-voltage characteristic as shown in FIG. 4, wherein when the current reaches a predetermined value or higher, a forward voltage becomes in a saturated state. This saturated voltage is on the order of 0.9 V to 1.3 V for a high-speed diode and on the order of 0.45 V to 0.55 V for a Schottky diode. As such, when the forward voltage of the commutation diode 63 is saturated, a power loss occurs, thereby posing a problem of deteriorating power-source conversion efficiency. Moreover, since the power loss becomes large and junction temperature of an element rises, there is a problem in which as the output current is larger, it is required to increase the number of commutation diodes 63 (for example, to two or three) for parallel connection and distribute a power loss per element, thereby suppressing the junction temperature.
To solve this problem, as shown in FIG. 5, one synchronous-rectification-type power supply device, in which a commutation MOSFET 3 (diode 3A) is used on a commutation side, has been known. In FIG. 5, the reference numeral “1” denotes a direct-current input power source, “2” a rectification MOSFET (diode 2A), “4” a choke coil, “5” an output capacitor, “6” a resistor depicting an LSI as a load, “7” an input capacitor, and “9” a control circuit. This uses the fact that, as shown in FIG. 6, a current-voltage characteristic of the diode is non-linear, whilst a current-voltage characteristic of the MOSFET may be linear depending on the gate voltage and thus is smaller in voltage drop than the diode.
In such a power supply device, there are parasitic components resulting from a circuit configuration shown in FIG. 7. For example, these components are a parasitic resistance 10 of a main circuit, a parasitic inductance 11 of the main circuit, a parasitic resistance 12 of a MOSFET gate driving circuit, and a parasitic inductance 13 of the MOSFET gate driving circuit. FIG. 8 depicts a relation between the parasitic inductance 11 of the main circuit and a power source loss. It can be seen that as the inductance increases, the loss increases. Similarly also for the parasitic resistance 10 of the main circuit, the parasitic resistance 12 of the MOSFET gate driving circuit, and the parasitic inductance 13 of the MOSFET gate driving circuit, there is a tendency that as their numerical values increase, their losses increase.
As a means for reducing the parasitic inductance 11 of the main circuit, there is a scheme of mounting a plurality of semiconductor chips on one package. This scheme is called a Multi Chip Module (MCM) or System in Package (SiP). In recent years, as shown in FIG. 9, a module, in which a driving unit 15, a rectification MOSFET 2, a commutation MOSFET 3 are integrated as a function block 16, has been commercially available and is described in detail in Japanese Patent Laid-Open Publication No. 2004-342735 (Patent Document 1).
FIG. 10 is a drawing shown in above Patent Document 1, wherein a rectification MOSFET 20, a commutation MOSFET 21, and a driving IC 22 are integrated in a Quad FlatNo-Lead (QFN) package and wire bondings 23 are used for connection between chips and for connection between the chip and a lead frame 24. FIG. 11 is a section view of FIG. 10 (taken along line a-a′).